Low-temperature in-plane coefficient of thermal expansion (CTE) testing evaluates the dimensional stability of IC package substrates across sub-zero temperature ranges, a critical parameter for solder joint reliability, warpage control, and thermal cycling performance in advanced semiconductor packaging. This article explains the applicable sample types, measurable test items, instrumentation and methods, industry standards, and typical applications of low-temperature package substrate CTE measurement.
Technical Overview
The in-plane coefficient of thermal expansion (CTE, symbolized as alpha) quantifies the fractional dimensional change of a package substrate in the X and Y directions per degree of temperature change, typically expressed in ppm/°C. Because a silicon die expands at only about 2.6 to 3.0 ppm/°C while organic laminate substrates typically expand at 10 to 17 ppm/°C, CTE mismatch is one of the dominant drivers of solder joint fatigue, delamination, and package warpage during thermal cycling. While most routine CTE characterization is performed between room temperature and 150 to 260 °C, many reliability specifications now demand data at sub-zero temperatures, since automotive, aerospace, and outdoor 5G infrastructure products must survive environments down to −40 °C, −55 °C, or even lower.
Low-temperature in-plane CTE testing therefore extends the measurement window downward, commonly covering ranges such as −55 °C to +150 °C or −70 °C to +25 °C, and in cryogenic configurations down to approximately −150 °C. The resulting data provides design engineers with tangent and secant CTE values used in finite element warpage simulation, coefficient-of-mismatch calculations, and lifetime prediction models such as Coffin–Manson. Testing is generally performed in accordance with recognized standards, including ASTM E831 (TMA), ASTM E228 (push-rod dilatometry), ASTM E289 (interferometry), ISO 11359-2, and IPC-TM-650 methods 2.4.24 and 2.4.24.1.
- Quantifies X/Y-direction dimensional stability of package substrates at sub-zero temperatures
- Supports CTE-matched material selection between silicon die, copper, and laminate systems
- Provides essential input data for warpage simulation and solder joint reliability modeling
- Verifies compliance with automotive, aerospace, and JEDEC thermal cycling requirements
Testing Samples
Organic Laminate Package Substrates
Bismaleimide triazine (BT) core substrates, Ajinomoto build-up film (ABF) substrates, FR-4 and FR-5 based laminates, and halogen-free low-CTE materials are the most frequently submitted sample types. These samples may be tested in bare laminate form or as finished substrates containing patterned copper traces, plated through-holes, and solder mask, provided that the copper architecture is representative of the production design.
Ceramic Package Substrates
Alumina (Al2O3), aluminum nitride (AlN), low-temperature co-fired ceramic (LTCC), and high-temperature co-fired ceramic (HTCC) substrates are tested to verify their inherently low and stable CTE values, typically between 4 and 8 ppm/°C, which closely match semiconductor die and support high-reliability hermetic packaging.
Glass Core and Emerging Substrates
Glass-core substrates for advanced 2.5D/3D packaging, polyimide flexible substrates, and embedded-trace or redistribution-layer samples are increasingly characterized at low temperature because their low and tailorable CTE (approximately 3 to 9 ppm/°C) makes them attractive for large-body flip-chip applications where warpage must be tightly controlled.
Sample Preparation and Conditioning
- Recommended specimen geometry: strips or coupons of 3 to 10 mm in length for TMA, or longer specimens up to 25 mm for dilatometry, machined with parallel faces
- Directional marking of specimens to distinguish machine (X) and transverse (Y) directions of the laminate weave
- Pre-test conditioning: baking at 105 °C for 1 to 2 hours or desiccator storage to remove absorbed moisture, which can otherwise distort expansion data
- Removal or documented retention of surface copper, since residual foil measurably suppresses the apparent in-plane CTE
Testing Items
Low-temperature in-plane CTE testing programs typically report the following measurable quantities, derived from a continuous expansion-versus-temperature curve acquired across the specified thermal window:
- Alpha-1 CTE (below Tg): the linear expansion coefficient over the low-temperature region, for example from −65 °C to +25 °C or 25 °C to 125 °C
- Alpha-2 CTE (above Tg): the expansion coefficient above the glass transition region, applicable to organic substrates
- Glass transition temperature (Tg), identified from the inflection point of the expansion curve
- Secant (mean) CTE over specified engineering intervals and tangent CTE at discrete temperatures
- Directional anisotropy data, comparing X-direction versus Y-direction expansion caused by glass fabric weave asymmetry
- Total percent expansion and delta-CTE values used directly as inputs for warpage and stress simulation models
Testing Methods
Thermomechanical Analysis (TMA)
TMA is the most widely used technique for package substrate CTE measurement. A flat specimen is placed between a quartz platform and a low-load expansion probe, and a cryogenic furnace or mechanical chiller coupled with liquid nitrogen cooling achieves sub-zero starting temperatures. Testing commonly follows ASTM E831 or IPC-TM-650 2.4.24, using a heating rate of 3 to 5 °C/min under nitrogen purge. The first heating ramp is often discarded to relieve residual stress and thermal history, and data is collected on the second ramp to ensure reproducibility. For in-plane measurement, specimens are oriented so that expansion along the X or Y axis is transmitted to the probe, or a dedicated lateral-expansion accessory is employed.
Push-Rod Dilatometry (ASTM E228)
A quartz or alumina push-rod dilatometer accommodates longer specimens, which improves resolution for low-expansion ceramics and glass substrates. A cryogenic furnace enables measurement from approximately −180 °C to elevated temperatures, making dilatometry the preferred method when very low starting temperatures or ultra-low CTE values must be resolved with high accuracy.
Strain Gauge Method (IPC-TM-650 2.4.24.1)
Bonded foil strain gauges measure in-plane expansion of larger coupons over engineering-relevant thermal ranges, including negative temperatures achieved inside an environmental chamber. This method is particularly useful for evaluating finished multilayer substrates with complex copper patterns, since the gauge integrates expansion over a representative circuit area rather than a small coupon.
Optical and Non-Contact Methods
Laser interferometry per ASTM E289 and digital image correlation (DIC) provide contactless measurement of full-field in-plane strain, eliminating probe loading artifacts on thin or flexible substrates. These methods are valuable for research-grade characterization and for validating FEA warpage models across wide low-temperature ranges.
Calibration and Data Reduction
- Instrument calibration against reference materials such as sapphire, Invar, fused silica, or certified copper standards spanning the full low-temperature range
- Baseline subtraction using an empty-holder or reference run to remove system expansion contributions
- Isothermal equilibration holds of 10 to 30 minutes at the starting temperature before ramping, ensuring uniform specimen temperature
- CTE computed as (1/L0) × (dL/dT), with secant values reported over customer-specified intervals
- Reported deliverables: raw expansion curves, alpha-1 and alpha-2 values, Tg, and interval CTE tables with measurement uncertainty
Applications
Low-temperature in-plane CTE data for package substrates directly supports product reliability and design optimization across the electronics industry:
- Automotive electronics qualification under AEC-Q100 and AEC-Q200, where modules must survive −40 °C to +125 °C or −55 °C to +150 °C thermal cycling profiles
- Aerospace, defense, and satellite systems requiring verified material behavior from cryogenic through elevated temperatures
- Flip-chip, ball grid array (BGA), and chip-scale package development, where CTE data feeds warpage simulation and underfill selection
- Advanced 2.5D/3D packaging with silicon interposers and glass cores, where CTE matching between die, interposer, and substrate governs assembly yield
- Optical and photonic packaging, where micron-level dimensional stability across temperature is essential for alignment retention
- Incoming material inspection, supplier qualification, and statistical process control for laminate and build-up film manufacturers
- Failure analysis, where unexpected CTE shifts reveal moisture uptake, incomplete cure, delamination, or material degradation
FAQ
What low-temperature range can be tested for package substrate in-plane CTE?
Standard testing typically covers −55 °C or −70 °C up to 150 °C. Dilatometers and TMA instruments equipped with liquid nitrogen cooling can extend the lower limit to approximately −150 °C to −180 °C for cryogenic and aerospace applications.
Which method is most accurate for in-plane CTE at low temperature?
For most organic substrates, TMA per ASTM E831 offers the best balance of accuracy, throughput, and small sample size, with typical repeatability of approximately 0.5 ppm/°C. For ceramics and glass substrates with very low CTE values, push-rod dilatometry or interferometric methods provide superior resolution.
How does copper content affect the measured in-plane CTE?
Copper expands at roughly 17 ppm/°C, so heavily patterned copper planes constrain and lower the apparent in-plane CTE of an organic substrate. Testing should therefore be performed either on the bare laminate or on a finished substrate with production-representative copper density, depending on the design question being answered.
What is the difference between alpha-1 and alpha-2 CTE?
Alpha-1 is the expansion coefficient below the glass transition temperature and represents the stiff, glassy state relevant to low-temperature service. Alpha-2 is measured above Tg, where polymer softening causes a significantly higher expansion rate, often two to four times the alpha-1 value.
Why is the first heating cycle sometimes discarded?
The first heating ramp relieves residual stresses from lamination, patterning, and specimen machining, and drives off residual moisture. Recording data on the second cycle ensures the reported CTE reflects the intrinsic, stabilized material behavior and improves inter-laboratory reproducibility.
How are low-temperature CTE results used in reliability engineering?
The measured alpha values are entered into finite element models to predict package warpage across the thermal cycle, and the CTE mismatch between die, interposer, substrate, and PCB is used in Coffin–Manson-type fatigue models to estimate solder joint life before qualification testing begins.